
ISD5008
Publication Release Date: Oct 31 2008
- 23 -
Revision 1.2
TABLE 8: CONFIGURATION REGISTER 0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
CFG
O
AIG1
AIG0
AIP
D
AXG1
AXG0
AXP
D
INS0
AOS2
AOS1
AOS0
AOPD
OPS1
OPS0
OPA1
OPA0
VLPD
ANA
IN
AMP
Gain
SET
(2
bits)
ANA
IN
Power
Down
AUX
IN
AMP
Gain
SET
(2
bits)
AUX
IN
Power
Down
INPUT
SOURCE
MUX
Select
(1
bit)
ANA
OUT
MUX
Select
(3
bits)
ANA
OUT
Power
Down
OUTPUT
MUX
Select
(2
bits)
SPKR
&
AUX
OUT
Control
(2
bits)
Volume
Control
Power
Down
NOTE: See details on following pages
TABLE 9: CONFIGURATION REGISTER 1
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
CFG1
VLS1
VLS0
VOL2
VOL1
VOL0
S1S1
S1S0
S1M1
S1M0
S2M1
S2M0
FLSO
FLD1
FLD0
FLPD
AGP
D
VOLUME
CONT.
MUX
Select
(2
bits)
VOLUME
CONTROL
(3
bits)
SUM
1
MUX
Select
(2
bits)
SUM
1
SUMMING
AMP
Control
(2
bits)
SUM
2
SUMMING
AMP
Control
(2
bits)
FILTER
MUX
Select
SAMPLE
RATE
(&
Filter)
Set
Up
(2
bits)
Filter
Power
Down
AGC
AMP
Power
Down
NOTE: See details on following pages